1. Field of the Invention
The invention relates to semiconductor package technology and more particularly to a bump pad structure for interconnection of electronic devices.
2. Description of the Related Art
In the microelectronics industry, the manufacturing of integrated circuits (ICs) typically comprises the fabrication and packaging of ICs. The IC dies or chips are packaged and electrically connected to external circuits, such as packaging substrate boards, printed circuit boards (PCBs) or other dies/chips by bump/bond pads thereon. In order to electrically connect the dies/chips to external circuits, wires and/or conductive bumps are typically applied. For example, conductive bumps are formed on the corresponding bump/bond pads of a die and then the die is flipped, thereby connecting the conductive bumps to corresponding contacts formed on an external circuit.
Recently, due to the continually increasing manufacturing costs and environmental factors, lead-free solders for conductive bumps are being used more and more. Such lead-free solders, however, may cause “white bumps” due to the migration to lead-free solders. “White bumps” is a term that refers to the issue of die/chip cracking due to translation of vertical stress when a die/chip is joined or due to other thermal processing procedures, after the die/chip is joined to the organic laminate, in a package. The white bump problem is particularly serious with lead-free C4 (Controlled Collapse Chip Connection) technology, due to the stiffness of the lead-free bump.
FIG. 1 is a cross section of a conventional bump pad structure 100 for a chip. The bump pad structure 100 includes an insulating layer 101, such as a low dielectric constant (k) material layer, having a multi-layered interconnect structure comprising metal layers 102, 104, 106, and 108 therein, which are separated from each other. Moreover, metal via plugs are disposed between the metal layers 102, 104, 106, and 108 and are electrically connected to the metal layers 102, 104, 106, and 108. The multi-layered interconnect structure is typically connected to electronic devices in a die/chip (not shown). A bump pad 112 is formed directly on the uppermost metal layer 108 of the multi-layered interconnect structure and is partially covered by a passivation layer 110. An under bump metallurgic (UBM) layer 114 is formed on the bump pad 112 exposed from the passivation layer 110 for the placement of a lead-free solder bump (not shown).
In such a bump pad structure 100, the bump pad 112 typically uses a large via 112a to contact the multi-layered interconnect structure and may cause huge vertical stress. In order to prevent the insulating layer 101 from damage due to the applied stress, at least two thick metal layers 106 and 108 are used. If only one thick metal layer is used, the huge stress applied may induce “white bumps” as mentioned above, reducing reliability of the device. However, the use of two thick metal layers may increase the manufacturing cost. Accordingly, there is a need to develop a novel bump pad structure which is capable of mitigating the aforementioned problems.